Image sensors have become ubiquitous. They are widely used in digital still cameras, cellular phones, security cameras, as well as, medical, automobile, and other applications. The technology used to manufacture image sensors, and in particular, complementary metal-oxide-semiconductor (“CMOS”) image sensors (“CIS”), has continued to advance at great pace. For example, the demands of higher resolution and lower power consumption have encouraged the further miniaturization and integration of these image sensors.
FIG. 1 is a circuit diagram illustrating pixel circuitry of two four-transistor (“4T”) pixel cells Pa and Pb (collectively pixel cells 100) within an image sensor array. Pixel cells Pa and Pb are arranged in two rows and one column and time share a single readout column line (bit line). Each pixel cell 100 includes a photodiode PD, a transfer transistor T1, a reset transistor T2, a source-follower (“SF”) or amplifier (“AMP”) transistor T3, and a row select (“RS”) transistor T4.
During operation, transfer transistor T1 receives a transfer signal TX, which transfers the charge accumulated in photodiode PD to a floating diffusion node FD. Reset transistor T2 is coupled between a power rail VDD and the floating diffusion node FD to reset the pixel (e.g., discharge or charge the FD and the PD to a preset voltage) under control of a reset signal RST. The floating diffusion node FD is coupled to control the gate of AMP transistor T3. AMP transistor T3 is coupled between the power rail VDD and RS transistor T4. AMP transistor T3 operates as a source-follower providing a high impedance connection to the floating diffusion FD. Finally, RS transistor T4 selectively couples the output of the pixel circuitry to the readout column line under control of a signal RS.
In normal operation, the photodiode PD and node FD are reset to the supply voltage VDD by temporarily asserting the reset signal RST and the transfer signal TX. The image accumulation window (exposure period) is commenced by de-asserting the transfer signal TX and permitting incident light to charge the photodiode PD. As photogenerated electrons accumulate on the photodiode PD, its voltage decreases (electrons are negative charge carriers). The voltage or charge on photodiode PD is indicative of the intensity of the light incident on the photodiode PD during the exposure period. At the end of the exposure period, the reset signal RST is de-asserted to isolate node FD and the transfer signal TX is asserted to couple the photodiode to node FD and hence the gate of AMP transistor T3. The charge transfer causes the voltage of node FD to drop from VDD to a second voltage indicative of the amount of charge (e.g., photogenerated electrons accumulated on the photodiode PD during the exposure period). This second voltage biases AMP transistor T3, which is coupled to the readout column line when the signal RS is asserted on RS transistor T4.
The conversion gain of pixel cells 100 is defined as the ratio (R) of the change in voltage ΔV at node FD after charge transfer to the change in charge ΔQ of photodiode PD.R=ΔV/ΔQ   (Equation 1)The capacitance of photodiode PD is determined by calculating the amount of charge Q stored for a given amount of voltage applied V.Q=C·V   (Equation 2)Combining equations 1 and 2, conversion gain (R) is inversely proportional to the capacitance of node FD.R=ΔV/ΔQ=ΔV/C·ΔV=1/C   (Equation 3)
In general, it is desirable to design pixel cells 100 to have a high conversion gain R to improve low-light sensitivity. For traditional image sensors, conversion gain can be increased by reducing the capacitance of the floating diffusion. However, as pixel cell sizes continue to shrink, pixel saturation or overexposure in bright environments is becoming more acute. Furthermore, as pixel sizes get smaller and smaller, shared structure pixels are widely used. For shared structure pixels, the floating node FD is connected to several transfer gates. Therefore, the shared structure pixel floating node capacitance cannot be very small. For large pixels, large transfer gates are necessary to avoid image lag and therefore the floating node capacitance cannot be very small. This limit on the size of the floating node capacitance makes it difficult to achieve a high conversion gain in large image sensor pixels.